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 IRF7313PBF datasheet 
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Mensagem IRF7313PBF datasheet

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64Mb H-die SDRAM Specification
54 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.3
August 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Revision History
Revision 1.0 (September, 2003)
鈥?Finalized
Revision 1.1 (October, 2003)
Deleted speed -7C and AC parameter notes 5.
Revision 1.2 (May, 2004)
鈥?Added Note 5. sentense of tRDL parameter
Revision 1.3 (August, 2004)
鈥?Corrected typo.
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
鈥?JEDEC standard 3.3V power supply
鈥?LVTTL compatible with multiplexed address
鈥?Four banks operation
鈥?MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
鈥?All inputs are sampled at the positive going edge of the system clock
鈥?Burst read single-bit write operation
鈥?DQM (x4,x8) & L(U)DQM (x16) for masking
鈥?Auto & self refresh
鈥?64ms refresh period (4K cycle)
鈥?Pb-free Package
鈥? RoHS compliant
GENERAL DESCRIPTION
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x
4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG鈥瞫 high perfor- mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No.
Orgainization
Max Freq.
Interface
Package
K4S640432H-UC(L)75
16Mb x 4
133MHz(CL=3)
54pin TSOP(II)
K4S640832H-UC(L)75
8Mb x 8
133MHz(CL=3)
K4S641632H-UC(L)60
4Mb x 16
166MHz(CL=3)
K4S641632H-UC(L)70
143MHz(CL=3)
K4S641632H-UC(L)75
133MHz(CL=3)
Organization
Row Address
Column Address
A0~A11
A0~A11
A0~A11
Row & Column address configuration
Package Physical Dimension
#54 #28
0.25 TYP
#1 #27
22.62 MAX
22.22 卤 0.10
0.875 卤 0.004
0.21 卤 0.05
0.008 卤 0.002
1.00 卤 0.10
0.039 卤 0.004
+0.075
1.20 MAX
0.10 MAX
0.71 (0.02 )
0.05 MIN
54Pin TSOP(II) Package Dimension
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Data Input Register
LWE LDQM
Column Decoder
Latency & Burst Length
LRAS LCBR LWE
Programming Register
LCAS LWCBR
Timing Register
CLK CKE CS RAS CAS WE L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
PIN CONFIGURATION (Top view)
x16 x8 x4
N.C DQ1
N.C DQ2
N.C DQ3
N.C VDD
VDD 1
VDDQ 3
VSSQ 6
VDDQ 9
N.C 10
DQ1 11
VSSQ 12
N.C 13
VDD 14
54 VSS
53 N.C
52 VSSQ
51 N.C
50 DQ3
49 VDDQ
48 N.C
47 N.C
46 VSSQ
45 N.C
44 DQ2
43 VDDQ
42 N.C
41 VSS
N.C DQ6
N.C DQ5
N.C DQ4
N.C VSS
N.C 15
40 N.C/RFU N.C/RFU
N.C/RFU
CAS RAS
CAS RAS
 WE 16
CAS 17
RAS 18
BA0 20
BA1 21
39 DQM
38 CLK
37 CKE
36 N.C
35 A11
CLK CKE
N.C A11
CLK CKE
N.C A11
A10/AP A10/AP
A10/AP 22
33 A8 A8 A8
A0 23
VDD 27
32 A7
28 VSS
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE Clock enable
A0 ~ A11 Address
CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11,
Column address : (x4 : CA0 ~ CA9, x8 : CA0 ~ CA8 , x16 : CA0 ~ CA7)
BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ X15 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.
No connection
/reserved for future use This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
Storage temperature
-55 ~ +150
Power dissipation
Short circuit current
Note : Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70掳C)
Parameter
Symbol
Supply voltage
VDD, VDDQ
Input logic high voltage
VDD+0.3
Input logic low voltage
Output logic high voltage
IOH = -2mA
Output logic low voltage
IOL = 2mA
Input leakage current
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is 鈮?3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is 鈮?3ns.
3. Any input 0V 鈮?VIN 鈮?VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23掳C, f = 1MHz, VREF =1.4V 卤 200 mV)
Symbol
RAS, CAS, WE, CS, CKE, DQM
Address
DQ0 ~ DQ3
Notes : 1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70掳C for x4, x8)
IL CC
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S6404(08)32H-TC**
4. K4S6404(08)32H-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70掳C for x16 only)
IL CC
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S641632H-TC**
4. K4S641632H-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
AC OPERATING TEST CONDITIONS (VDD = 3.3V 卤 0.3V, TA = 0 to 70掳C)
Parameter
AC input levels (Vih/Vil)
2.4/0.4
Input timing measurement reference level
Input rise and fall time
tr/tf = 1/1
Output timing measurement reference level
Output load condition
See Fig. 2
Vtt = 1.4V
VOL (DC) = 0.4V, IOL = 2mA
Output
Z0 = 50鈩? (Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
tDAL(min)
2 CLK + tRP
Last data in to new col. address delay
tCDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid output data
CAS latency = 3
CAS latency = 2
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid output delay
CAS latency=3
CAS latency=2
Output data hold time
CAS latency=3
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output in Hi-Z
CAS latency=3
CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Output rise time
Measure in linear region : 1.2V ~ 1.8V
Volts/ns
Output fall time
Measure in linear region : 1.2V ~ 1.8V
Volts/ns
Output rise time
Measure in linear region : 1.2V ~ 1.8V
Volts/ns
Output fall time
Measure in linear region : 1.2V ~ 1.8V
Volts/ns
Notes : 1. Rise time specification based on 0pF + 50 鈩?to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 鈩?to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
133MHz Pull-up
0.5 1 1.5 2 2.5
Voltage
IOH Min (133MHz)
IOH Max (133MHz)
IOL Characteristics (Pull-down)
133MHz Pull-down
0 0.5 1 1.5 2 2.5
Voltage
IOL Min (133MHz) IOL Max (133MHz)
VDD Clamp @ CLK, CKE, CS, DQM & DQ
Minimum VDD clamp current
(Referenced to VDD)
0 1 2 3
Voltage
VSS Clamp @ CLK, CKE, CS, DQM & DQ
Minimum VSS clamp current
-2 -1 0
Voltage
SIMPLIFIED TRUTH TABLE (V=Valid, X=Don鈥瞭 care, H=Logic high, L=Logic low)
Command
A9 ~ A0
Register
Mode register set
OP code
Refresh
Auto refresh
Self refresh
Bank active & row addr.
Row address
Read &
column address
Auto precharge disable
Column address
Auto precharge enable
Write &
column address
Auto precharge disable
Column address
Auto precharge enable
Burst stop
Precharge
Bank selection
All banks
Clock suspend or active power down
Precharge power down mode
No operation command
Notes : 1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)


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